In circuits in which the power losses are low, in particular monolithically integrated circuits, the only circuit blocks in the circuit which are frequently switched on are those which are required to ensure the circuit operation at that time. Those circuit blocks which are not required are switched off. Particularly in the case of battery-powered appliances, in which circuits with low power losses such as these are used, this increases the time for which the appliances may be operated.
In order to switch off the circuit blocks which are not required, these circuit blocks can be deliberately decoupled from the supply voltage. When the circuit blocks are required for a specific function of the circuit, they are recoupled to the supply voltage. Electronic switching means, in particular MOSFET transistors (Metal Oxide Semiconductor Field Effect Transistors), are used for coupling purposes, and are arranged between one pole of the supply voltage and the corresponding supply connection of the circuit block.
In general, switching means such as these must be designed such that only a small voltage drop occurs across the switching means during operation of that part of the circuit, so that the supply voltage which is effectively applied to the circuit block is reduced only slightly. This means that the electrical resistance of the switching means when in the switched-on state Ron must be as small as possible, particularly in the case of large quiescent supply currents or large mean supply currents. Transistors used as switching means therefore have very large areas. In a MOSFET transistor with a correspondingly large area, there is a small resistance RT,on between the drain connection and the source connection when the transistor is in the switched-on state. One disadvantage of a MOSFET transistor with a correspondingly large area is its large parasitic capacitances, whose charge must first of all be changed when the MOSFET transistor is switched on. When the MOSFET transistor is switched on, it briefly requires a very high charge-changing or charging current from the supply voltage. The briefly very high charging current results in an additional voltage being dropped across resistances located upstream of the input of the switching means and in the direction of the pole of the supply voltage, in particular parasitic resistances such as the internal resistance of the supply voltage or the resistance of the bonding wire for the supply voltage, thus interfering with other circuit blocks which are being operated and are fed via the same voltage supply. In this case, the effective available supply voltage for these circuit elements is briefly reduced, thus reducing the signal-to-noise ratio for digital circuits. In this case, circuit blocks which are placed densely on the switch and on the circuit block to be switched on are particularly subject to interference since, in the layout of a monolithically integrated circuit, these frequently have a common supply voltage path, which is formed via resistive metallization, with a corresponding line resistance. If this voltage drop relates to the earth of the supply voltage, this is referred to in American English as a so-called “ground bounce”.
The charging process may be extended over a longer time period, in order to reduce the maximum charging current. In this case, the maximum charging current is reduced. This can be done by using a large number of corresponding smaller transistors arranged in parallel instead of one switching means comprising a large-area transistor, for example four transistors connected in parallel. These smaller transistors are switched on successively in order to switch on the circuit block. In this case, the time which passes while the transistors are being switched on ensures that the drive for the transistor which is in each case being switched on at a later time is delayed by using an appropriate delay element with a fixed time delay with respect to the drive for the transistor which is switched on before it. A procedure such as this has the disadvantage that the time delay caused by the delay elements is generally shorter, assuming an acceptable degree of circuit complexity, than the time delay which is governed by the time constant of the parasitic element involved in the switching-on process, such as the line resistance of the supply voltage feed and the effective network capacitance of the supply voltage node upstream or downstream of the group of transistors. The influence in terms of reducing the maximum charging current is therefore frequently insufficient. The maximum charging current can admittedly be reduced considerably by increasing the number of parallel-connected transistors and delay elements or the delay per delay element, but a measure such as this increases the circuit complexity. Furthermore, in principle, the delay of a switch such as this formed from a large number of parallel-connected transistors must be matched to the respective circuit element to be driven via this switch, since the time constant of the switching-on process is dependent on the circuit element to be driven, and its layout. It is therefore also very time-consuming to design a switch such as this.